1. Field of the Invention
This invention relates to methods of fabricating field-effect semiconductor devices and more particularly to a method of providing IGFET devices having junction depths of less than one micron which can sustain high voltages while possessing low sheet resistivity and low capacitance.
2. Description of the Prior Art
Traditionally, n-channel IGFET source/drain junctions have been formed by thermal solid state diffusion techniques using various dopant sources. Recent trends to reduce the horizontal geometry of such devices have also required that vertical geometries also be reduced along with corresponding reductions in operating potentials and power. Very large scale integration techniques require IGFET junction depths on the order of 0.2 to 1.0 micron. Solid state diffusion techniques have proved to be unsuitable for the formation of such junctions because of a number of undesirable characteristics including the inability to provide adequately low sheet resistance with the required junction depths. In addition, impurity concentration profiles resulting from surface diffusion are often inadequately steep and result in increased junction capacitance as well as increased reverse bias leakage levels. Ion implantation is now preferred for providing source/drain regions in IGFETs as ion implantation enables better selection of impurity species, more accurate control of impurity concentration and profile and is particularly adapted to self-aligned processing techniques.
The use of ion implantation as a doping technique causes physical damage to the semiconductor crystal and thermal annealing of the implanted crystal becomes of prime importance in any ion implantation process. Remaining or residual damage, when made electrically active by precipitation effects can enhance reverse bias junction leakage if these defects lie near the p-n junction depletion region. A preferred technique, therefore, has been to utilize ion implantation as a prediffusion source and to follow the ion implantation with a thermal diffusion/anneal process in order to enable the dopant species to diffuse beyond damaged crystal sites and become electrically active. Implant/diffusion processes are particularly important in those instances when a screen oxide is used to protect the silicon semiconductor surface from implant-introduced surface contamination, which provides an additional defect producing phenomenon caused by the presence of excess oxygen atoms in the crystal.
As a result of numerous experiments arsenic has become the preferred n-type dopant species for making source/drain regions of n-channel polysilicongate IGFETs, primarily because of the ability to achieve relatively low resistivity shallow junction having low leakage characteristics in a simple implant/diffusion process.
The reduction of device geometries also has some inherent limitations. For example, the reduction in device size, particularly channel length, causes a decrease in the drain voltage at which low-level avalanche, junction breakdown and/or punch-through occur, see for example the article, "Drain Voltage Limitations of MOS Transistors," I. M. Bateman et al., Solid-State Electronics, Vol. 17, pp. 539-550 (June 1974). Such drain voltage limitations impose restrictions on the design of IGFET devices with respect to one or more of: drain voltage supply, channel length, diffusion depth, diffusion concentration profile, substrate doping level, channel doping level, etc.
Although many applications for very large scale integrated circuits often utilize the inherent advantage of lower supply voltages, current processes are normally designed to operate properly at a drain voltage supply source of 5 volts or less. However, in certain applications such as in performance driven designs and in electrically programmable read only memories, it is desirable to provide a process which is tolerant of higher level supply voltages.
As described above, the primary concern relating to source/drain region design is the ability to withstand various breakdown phenomena and to provide low leakage current.
For example, as described in U.S. Pat. No. 3,798,079 to Chu et al., it is known that the avalanche breakdown voltage of a p-n junction can be increased by providing a flattened dopant concentration profile by the simultaneous thermal diffusion of two elements of the same dopant type but having different diffusion rates such that the faster diffusing element is driven deeper into the substrate than that of the slower. Such simultaneous surface diffusion techniques have also been used to control the concentration profile of the buried side of a p-n junction in order to control the capacitance of a p-n junction, as taught by U.S. Pat. No. 3,840,306 to Raabe et al. Similar results can also be achieved by sequential ion implantation/diffusion processes using the same impurity element as taught by U.S. Pat. No. 4,106,953 to Onodera. Such techniques although providing some degree of control of the dopant concentration profile are suitable only for forming p-n junctions having a depth of several microns, many times greater than that required for very large scale integrated circuit devices.
Multiple dopant diffusion techniques for reducing low level avalanche conditions at the drain electrode of IGFET devices are also known which rely on control of the dopant concentration profile at the drain end of the channel of an IGFET. U.S. Pat. No. 4,028,717 to Joy et al. teaches a drain junction formed from concentric diffusions or ion implantation regions. A first low concentration region formed with a maximum concentration below the semiconductor surface effectively forms the drain electrode. A second high concentration region lies inside the first region and has a concentration peak near the semiconductor surface to provide a low resistivity contact to the first region. The two regions are defined separately and require separate mask and photoresist steps. U.S. Pat. No. 4,070,687 to Ho teaches a similar approach to the same problem but uses only one masking step. Here two dopants, arsenic and phosphorus are diffused or ion implanted to provide a high surface concentration and subsequently diffused to form an n+, p-, p junction due to the difference in diffusion rates.
U.S. Pat. No. 3,897,276 to Kondo may also be of interest as it teaches a double ion implantation method of forming a junction from as-implanted ions without subsequent diffusion in which a p+, p, n, n+ junction is formed in a semiconductor substrate. Ions of a relatively high atomic mass, indium, are implanted at a low concentration relatively deep below the surface of a silicon substrate and at least one implant of a low mass ion, boron, of the same impurity type is implanted with a high concentration near the surface of the substrate to form an IMPATT diode. The p-n junction portion of the device is controlled by the smaller straggling range of the heavier ion in the substrate and thus provides a step-like concentration profile at the metallurgical junction.
The article "Emitter Structure with Different Impurity Concentrations" by B. K. Aggarwal, IBM Technical Disclosure Bulletin, (19) 1, pp. 162-3 (June 1976) and the article referenced therein, "A Novel Bipolar Device with Low Emitter Impurity Concentration Structure," by H. Yagi et al., Technical Digest 1974 International Electron Devices Meeting, Dec. 9, 10 and 11, 1974, pp. 262-265, also may be of interest. These articles relate to methods of forming NPN bipolar transistor devices which have a n+, n, p+, n junction structure. Yagi et al., teaches the formation of the n+, n emitter region by the thermal diffusion of a high concentration of phosphorus into a 2 ohm-centimeter n-type epitaxial layer. Aggarwal suggests three alternative techniques for forming the emitter of Yagi et al. A first, similar to Onodera above, uses sequential implantation and anneal steps of a shallow high concentration of arsenic followed by a deeper high concentration of phosphorus resulting in a composite n-type emitter at least several microns in depth. The second uses a single shallow implantation step of a high concentration of arsenic followed by thermal diffusion of a high concentration of phosphorus. The third uses the combination of the first alternative but is annealed in a standard bipolar drive-in environment.
Other two-specie ion implantation junction forming techniques are also known, particularly for reducing the effects of ion implant caused defects and crystal lattice strain. For example MacIver and Greenstein in their U.S. Pat. Nos. 4,133,701; 4,133,704 and 4,144,100 respectively teach enhancing the diffusion depth of phosphorus in bipolar transistors by implanting phosphorous regions with a halogen to create an amorphous surface prior drive-in; providing low leakage p-n junctions by implanting an inert specie to amorphize the surface prior to drive-in in a wet oxidation atmosphere; and forming low leakage, low concentration n-p junctions by ion implanting halogens or silicon to amorphize the doped surface prior to a wet oxidation drive-in.
U.S. Pat. No. 3,812,519 to Nakamura et al. is of interest as it relates to ion implantation techniques for forming high concentration bipolar emitter regions having reduced emitter dip effect by the surface diffusion of both arsenic and phosphorous having a concentration ratio, of arsenic to phosphorus atoms of from 4 to 40:100. The presence of the arsenic is intended to prevent lattice collapse, thus allowing a higher surface concentration to be achieved. U.S. Pat. No. 4,111,719 to Mader et al. teaches achieving a similar result in which a silicon substrate which has been ion implanted with arsenic at 80 KeV with a dose of 2.times.10.sup.16 ions/cm.sup.2 (hereafter such powers of 10 will be expressed as 2E16 ions/cm.sup.2), resulting in a peak concentration of arsenic near the solid solubility of arsenic in silicon, is also implanted with germanium at a dose of 2E15 ions/cm.sup.2 at 75 KeV and then annealed.
In summary, while the prior art teaches a variety of junction formation techniques both to provide controlled dopant concentration profile for various types of devices and to provide improved junction quality by reduction of leakage causing defects of the crystalline structure in the vicinity of junctions, the fabrication of shallow junctions of less than one micron depth with adequate low resistivity, high breakdown voltage, high sustaining voltage, low capacitance and low reverse bias leakage suitable for use in forming junctions in very large scale integrated circuit IGFET devices has not been provided.